1. Field of the Invention
This invention relates to stored program digital computer systems and more particularly to data transfer control apparatus for controlling the transfer of data between I/O devices and the CPU.
The invention finds particular utility in stored program computer systems where the data transfers are to take place asynchronously. Asynchronous data transfers generally simplify the complexity of the I/O attachment logic but place a heavier burden on the port or channel for synchronization and de-synchronization of the I/O devices for data transfer operations.
The present invention simplifies the synchronization and de-synchronization control apparatus by using fewer interlock lines and provides flexibility to accommodate the different timing requirements of the I/O devices and to accommodate multi-device responses. Constant polling requirements are eliminated because devices requesting service switch the hardware into a predefined state and while in that state, the port can by way of an I/O instruction (Multidevice Command) transfer the service request state of devices into the CPU for analysis.
2. Description of the Prior Art
In the past it was not uncommon to require an I/O device to respond at a precise time rather than at any time during a predetermined time interval as in the present invention. In those systems where data transfers take place asynchronously, the I/O device address would be sent out and the CPU would require a response before sending out the I/O command. Such an arrangement is more time consuming and complex than in the present invention where the I/O address and command are sent out simultaneously to the I/O attachment. U.S. Pat. Nos. 3,336,582 for "Interlocked Communication System" dated Aug. 15, 1967, and 3,377,619 for "Data Multiplexing System" dated Apr. 9, 1968, are representative of such prior art.